4-20 mA interface circuit

ABSTRACT

A 4–20 mA interface circuit is disclosed having a resistor in series with a DC/DC converter, and further having a current bypass circuit in parallel to the series combination of the resistor and DC/DC converter. In this way, a 4–20 mA analog current at a low frequency may be bypassed around the series combination, whereas a high-frequency current carrying a digital communications signal may be presented with the resistor as its only effective input impedance. In this way, the 4–20 mA current sees an input impedance which allows the 4–20 mA current to be used in supplying power to an external device, whereas the high-frequency current sees an impedance which allows a reliable, low-distortion reading of the digital communications signal therefrom. The high-frequency current may be superimposed on the 4–20 mA, low-frequency current. Portions of the 4–20 mA current not required to power the external device may be shunted to ground, or may be driven back through the DC/DC converter, to thereby present a negative impedance to the 4–20 mA current.

TECHNICAL FIELD

This invention relates to industrial control systems.

BACKGROUND

Conventional industrial control systems allow control of remote fielddevices, such as a valve positioner controlling a fluid flow. Forexample, such a field device may set a position of the valve rangingfrom “closed” to “open” (i.e., 0%–100%) based on a current value,ranging, for example, from 4–20 mA provided to the positioner. In suchsystems, the valve position may vary in direct relation to the current,thus being fully closed at 4 mA and fully opened at 20 mA. The currentmay be sent from a control system via a two-wire interface, and receivedat an interface circuit at the field device that converts the analogcurrent signal to a digital signal, which is then analyzed by aprocessor and applied to adjust the valve position as just described.

The control system is often remote from the field device, and connectedonly via the two-wire interface. Therefore, conventional industrialcontrol systems often supply power to the field device via the sametwo-wire interface. The available power may be, for example, a currentvalue of the 4–20 mA control current multiplied by the loop inputvoltage at the input of the field device.

In addition to the 4–20 mA analog control signal, conventionalindustrial control systems gain additional control over the field deviceby adding a digital communications signal to the analog control signalalready present on the two-wire interface. The digital communicationssignal can be used to monitor secondary variables and other data thatcan be used for tasks including operations, commissioning, maintenance,and diagnostic purposes.

Specifically, for example, a digital communications signal can be addedto the 4–20 mA control signal using the Highway Addressable RemoteTransducer (“HART”) protocol. The HART protocol uses a Frequency-ShiftKey (“FSK”) modulation technique. Advantageously, the HART protocol isfunctional in the low-power environment provided by the use of the 4–20mA control signal for power (resulting in available power in the mWrange), and is otherwise compatible with (and therefore easilyretrofitted to) existing industrial control systems.

Thus, conventional industrial control systems may provide a 4–20 mAanalog control signal, a digital communications signal, and electricalpower to a remote field device, all via a two-wire interface.Conflicting requirements of these three signals, along withcharacteristics of conventional industrial process control settings, maylead to various challenges in implementing robust industrial controlsystems.

SUMMARY

According to one general aspect, a circuit includes a two-wire interfaceoperable to input a low-frequency, first current and a high-frequency,second current, a first impedance presented to the first current, asecond impedance presented to the second current, a DC supply circuit inseries with the second impedance to thereby form a series combination,and a current bypass circuit in parallel with the series combination andoperable to bypass a portion of the first current around the seriescombination.

Implementations may include one or more of the following features. Forexample, the first impedance may be a sense resistance operable totransmit the first current, such that a device variable of a deviceexternal to the circuit is set according to a sense voltage across thesense resistance and proportional to the first current.

The first impedance may be in series with the parallel combination ofthe current bypass circuit and the series combination. The firstimpedance may be additionally presented to the second current. Thesecond impedance may include a passive resistive element. The DC supplycircuit may be a DC/DC converter operable to drive current forwards andbackwards therethrough.

The portion of the first current may be determined based on a differencebetween a magnitude of the first current and an amount of drive currentrequired to drive a load device. The current bypass circuit may beoperable to maintain a stable DC voltage at the two-wire interface.

The portion of the first current may be determined based on a magnitudeof the first current, thereby forming a pre-determined relationshipbetween an output current of the circuit and the first current. In thisimplementation, the magnitude of the first current may be measured atthe first impedance. An input voltage measured at the two-wire interfacemay increase with a decrease in the first current. Further, the circuitmay present a negative impedance at the two wire interface, and theportion of the current may be driven through the DC supply circuit andoutput through the two-wire interface.

The first current may have a frequency below approximately 500 Hz. Thesecond current may be super-imposed over the first current and carries adigital communications signal.

According to another general aspect, a circuit may include a resistanceoperable to determine an impedance seen by a circuit input current whenthe circuit input current is above a determined frequency, a DC-DCconverter in series with the resistance to thereby form a seriescombination of the resistance and the DC-DC converter, and a bypasscircuit in parallel to the series combination, the bypass circuitoperable to route a portion of the circuit input current around theseries combination when the circuit input current is, below thedetermined frequency.

Implementations may include one or more of the following features. Forexample, the resistance may include a passive element, such as aresistor. The DC-DC converter may be further operable to input a firstvoltage and output a second voltage that is lower than the firstvoltage.

The bypass circuit may be further operable to draw excess current thatexceeds a predetermined level in magnitude and redirect the current awayfrom the circuit output. In this implementation, the bypass circuit mayredirect the excess current to ground. Alternatively, the bypass circuitmay redirect the excess current into an output of the DC-DC converter,and thereby compensate a voltage drop along a two-wire loop carrying thecircuit input current to the circuit. In this case, the excess currentmay exit the input of the DC-DC converter, traverse the resistance, andbe output from the circuit to thereby present a negative impedance tothe circuit input current when the circuit input current is below thedetermined frequency.

The DC-DC converter may be further operable to pass current from aninput of the DC-DC converter to an output of the DC-DC converter, and topass current from the output to the input. The portion of the circuitinput current may be shunted to ground, and an input voltage to thecircuit may be maintained at a stable value.

The portion of the circuit input current may be used to drive a devicethat is external to the circuit.

The circuit may also include a sense resistance operable to input thecircuit input current, whereby a sense voltage proportional to thecircuit input current and taken across the sense resistance may be usedto set a device variable for a device external to the circuit. In thiscase, the sense voltage may further determine an input voltage to thecircuit, such that the input voltage decreases with an increase in thecircuit input current. Further, a reverse current output by the bypasscircuit and not required by the device may be output from the circuitvia the DC/DC converter and the resistance, to thereby present anegative impedance to the circuit input current when the circuit inputcurrent is below the determined frequency.

According to another general aspect, a circuit may include a firstimpedance, a second impedance, a DC/DC converter in series with thesecond impedance and forming a series combination, and a current bypasscircuit in parallel to the series combination and operable to presentthe first impedance to a low-frequency, 4–20 mA first current, andfurther operable to present the second impedance to a high frequencysecond current, the second current carrying a digital communicationssignal and superimposed on the first current.

Implementations may include one or more of the following features. Forexample, the first impedance may include a sense resistor. The currentbypass circuit may present both the first impedance and the secondimpedance to the second current.

The first impedance may include a negative impedance resulting from areverse current driven from the current bypass circuit through the DC/DCconverter and the second impedance. In this case, a magnitude of thereverse current may be based on a voltage across a sense resistor, thevoltage being proportional to the first current.

A portion of the first current may be used to power a device external tothe circuit. In this case, a portion of the first current not requiredto power the device may be shunted to ground by the current bypasscircuit, thereby maintaining a circuit input voltage at a stable value.

The details of one or more implementations are set forth in theaccompanying drawings and the description below. Other features will beapparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of an industrial control system.

FIG. 2 is a circuit diagram of a first interface circuit.

FIGS. 3A and 3B are impedance versus frequency graphs for the circuitsof FIGS. 2 and 4.

FIG. 4 is a circuit diagram of an implementation of the interfacecircuit of FIG. 2.

FIG. 5 is a circuit diagram of a second interface circuit.

FIG. 6 is an impedance versus frequency graph for the circuits of FIGS.5 and 7.

FIG. 7 is a circuit diagram of an implementation of the interfacecircuit of FIG. 5.

FIGS. 8A and 8B are impedance versus frequency graphs for the circuit ofFIG. 7.

FIG. 9 is a circuit diagram of a third interface circuit.

FIG. 10 is an impedance versus frequency graph for the circuits of FIGS.9 and 12.

FIG. 11 is a voltage versus current graph for the circuits of FIGS. 9and 12.

FIG. 12 is a circuit diagram of an implementation of the interfacecircuit of FIG. 9.

FIGS. 13A and 13B are impedance versus frequency graphs for the circuitof FIG. 12.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of an industrial control system 100. In FIG.1, a controller 102 modifies a 4–20 mA current output by a currentsource 104, based on input from an external system and powered by avoltage source 106, which may be, for example, a 24V voltage source.

The controller 102 outputs a certain set value “w,” ranging from 4–20mA, over a two-wire interface 108. The set value w is received at afield device 110 such as, for example, a valve positioner. Of course,the field device could be any one of a number of field devicescompatible with the techniques described herein, such as, for example,field devices controlling an external temperature, fluid level, or otherprocess variable.

Valve positioner 110 outputs a pressure P_(y) to a pneumatic actuator112, which in turn sets a position of a valve 114 ranging from “fullyclosed” to “fully open.” More specifically, field device 110 receivesthe set value w via the two-wire interface 108, and is protected fromany excessive voltage fluctuations by the combination of, for example, aresistor 116 and a zener diode 118.

An interface circuit 120 receives the set value defined by the set valuew from the controller 102, and, as discussed in more detail below,forwards the set value w to a processor 122. Processor 122 digitizes thesignal and forwards the digitized signal to a current-to-pressuretransducer 124, which outputs a corresponding pressure P_(s) to apressure amplifier system 126. The pressure amplifier 126 amplifies thepressure P_(s) to a larger pressure P_(y), and outputs P_(y) to thepneumatic actuator 112.

A position converter 128, such as a potentiometer, senses the actualvalue of the valve position, and feeds this value to the processor 122for any necessary adjustments. The processor 122 compares the actualvalue to the set value w and makes any necessary adjustments using anynumber of feedback control techniques.

A communicator 130 is connected to the two-wire interface 108, andallows a user to monitor and/or control an operation of the field device110. The communicator 130 includes a display 132 and an input means,such as, for example, buttons 134.

As explained above, digital communications may be transmitted thetwo-wire interface 108 simultaneously with the 4–20 mA control signal.Such communications may be transmitted/received by any of the controller102, the field device 110, and the communicator 130. As described above,the 4–20 mA current is multiplied by a loop input voltage at the meetingof the two-wire interface with the interface circuit 120 of the fielddevice 110 and provides electrical power to the field device, to therebypower, for example, the transducer 124 and the processor 122.

In FIG. 1, various elements which may be used in conjunction with thefield device 110 are not shown, for the sake of clarity. For example, amodem such as a HART modem may be utilized to mediate the high-frequencydigital communications between the interface circuit 120 and theprocessor 122. As another example, a display element, such as alight-emitting diode (“LED”) array, may be used at the field device 110to provide a user with information about an operating status of thefield device 110.

Issues to be considered in implementing systems such as system 100 arethe impedance characteristic(s) of the system and the powercharacteristic(s) of the system, as well as their overlapping effects onone another. For example, the 4–20 mA current, which is essentially a DCcurrent, should see very low or zero impedance at the interface circuit120 of field device 110. This is due to the fact that the field device110 should have enough power available to operate at least the actuator112 and the processor 122, even at the lowest current setting of 4 mA.On the other hand, there will be times when the current available to thefield device 110 will be larger than 4 mA (since the current may rangeup to 20 mA), which may result in an excessive DC terminal voltage andthe possibility of excessive heat and/or short circuits.

In order to meet both of these conditions, field device 110 shouldgenerally present a very low impedance to the low-frequency DC current.Even then, additional voltage control may be necessary to provide safeand reliable operation of the system 100, as discussed below.

In contrast to the impedance requirement at low frequencies,high-frequency signals carrying the digital communications from, forexample, communicator 130, require a relatively high impedance.Moreover, this communications impedance should be essentially flat overthe communication frequency band, so as to avoid distortion of themultiple frequency components contained within the digitalcommunications signal. The communication frequency band may be, forexample, 500 Hz–5 kHz or 500 Hz–10 kHz.

FIG. 2 is a circuit diagram of an interface circuit 200 corresponding tothe interface circuit 120. A specific example of an implementation ofcircuit 200 is described in more detail in U.S. patent application Ser.No. 09/496,667, which is hereby incorporated by reference in itsentirety. FIG. 2 is an abstract or simplified representation of such acircuit that might implement much of the functionality described abovewith respect to interface circuit 120.

In FIG. 2, interface circuit 200 has an input voltage U_(i) acrosspositive and negative terminals 202 and 204, respectively. Zener diodes206 and 208 imply voltage regulation which takes some fraction of theinput voltage U_(i) and outputs this fraction as an output voltageU_(o), which is used to power circuitry including processor 122 andactuator 112. Excess output voltage is sinked to ground, as shown. Thezener diodes 206 and 208 thus represent a power supply (and regulation)circuitry 210.

In series with this power supply circuitry 210 is an impedance controlcircuit 212, which includes an inductance 214, a resistance R_(k) 216,and a sense resistor R_(s) 218. Inductance 214 may imply the electricalcharacteristic of inductance, rather than a literal inclusion of aninductance coil. Resistance R_(k) 216 may imply the communicationsimpedance presented to digital communications received at the circuit200, and may be, for example, on the order of 200 Ohms–1 kOhms. Senseresistor R_(s) should be relatively low, on the order of, for example,10–50 Ohms.

The sense resistor R_(s) 218 is included in series with the parallelcombination of inductance 214 and resistance Rk 216, as shown. The senseresistor 218 provides a voltage measurement proportional to the receivedcurrent, and thereby allows measurement of the current. Accordingly,current is transmitted via the negative terminal to, for example, ananalog-to-digital (“ADC”) converter (not shown) for conversion of acurrent value of the 4–20 mA signal to a digital value for use byprocessor 122. Similarly, high-frequency components of the current maybe detected by, for example, a HART modem, which, as mentioned above,may modulate/demodulate such signals for transmitting/receiving digitalcommunications in conjunction with processor 122.

FIGS. 3A and 3B are impedance versus frequency graphs for the circuitsof FIGS. 2 and 4. In FIG. 3A, as shown, an impedance of power supplycircuitry 210 is essentially zero at all frequency ranges. In FIG. 3B, aDC portion of a current received at terminals 202 and 204 will see ashort circuit with respect to inductance 214, and will bypass resistanceR_(k) 216 entirely, seeing only R_(s) 218 as a resistance. In contrast,an AC signal at a sufficiently high frequency will begin to see aportion of resistance R_(k) 216 in series with R_(s) 218, until, atsufficiently high frequencies, R_(k) combined with R_(s) the resistanceseen by the digital communications signal. R_(k)+R_(s) thus provides aflat impedance for a sufficiently wide frequency range (e.g. 500 Hz –5kHz).

FIG. 4 is a circuit diagram of an implementation 400 of the interfacecircuit 200 of FIG. 2. In FIG. 4, a circuit 400 includes a power supplycircuit 402, a DC output voltage control circuit 404, and an impedancecontroller circuit 406. The power supply circuit 402 includes a DC/DCconverter 408, which inputs a loop input voltage across terminals 202and 204, and outputs a voltage U_(o) which is some fraction of the inputvoltage.

An example of such a DC/DC converter 408 is discussed incommonly-assigned U.S. Pat. No. 6,064,583, which is hereby incorporatedby reference. As described therein, such a DC/DC converter has arelationship between an input voltage U_(i) and an output voltage U_(o)such that (n×U_(o))=U_(i); e.g., for a 9V input, an output for n=3 wouldbe 3V. The value “n” may be determined by a user for a particularapplication, based on available input voltages and DC/DC converters.Additionally, such a DC/DC converter 408 has the characteristic ofbi-directional current flow; that is, current may flow from an input toan output of the DC/DC converter, or may flow from the output to theinput of the DC/DC converter. Other DC/DC converters having similarcharacteristics could also be used.

The DC output voltage control circuit 404 includes a current sink 410,which may be, for example, a transistor. The DC output voltage controlcircuit 404 further includes a resistor 412, a resistor 414, and anoperational amplifier 416, as shown. In an operation, the DC outputvoltage control circuit 404 detects a current higher than the minimuminput current 4 mA. If this excess current is required by the loaddevice to increase the supplied power, then the excess current issupplied to the load (e.g., actuator 112) accordingly. Excess currentnot used at the load may be, for example, sinked to ground, so as tomaintain the output voltage U_(o) at some predetermined (safe) level.Such a current bypass circuit is described in, for example,commonly-assigned U.S. Pat. No. 6,064,582, which is hereby incorporatedby reference in its entirety.

The impedance control circuit 406 includes sense resistor 218, whichprovides for current sensing of the 4–20 mA signal. A plurality ofelements including a resistor 418, a resistor 420, a resistor 422, aresistor 424, a resistor 426, a resistor 428, a capacitor 430, acapacitor 432, and a capacitor 434 are all connected so as to provide afilter that is operable to detect the approximately 1 mA peak-to-peakcurrent fluctuations overlying the 4–20 mA current signal whichrepresent digital communications from, for example, communicator 130.When such digital communications are detected, an operational amplifier436, which is powered by voltages determined at resistor 218 R_(s) and aresistor 438 R_(c), operates to determine an impedance seen by thecircuit 400.

More specifically, an AC impedance Z of circuit 400 can be expressed interms of a first impedance Z₁=R_(g)+[R_(d)∥(R_(e)+1/jwC_(a)))] and asecond impedance Z₂=R_(j)+1/(jwC_(b)), such thatZ=R_(s)/[1−[Z₁/(Z₁+Z₂)]*(R_(g)+R_(h))/R_(g)+R_(s)/(Z₁+Z₁+Z₂)], whereR_(g) is resistor 424, R_(d) is resistor 418, R_(e) is resistor 420,C_(a) is capacitor 430, R_(j) is resistor 428, C_(b) is capacitor 432,R_(h) is resistor 426, and j represents the mathematical constant √−1.Thus, a value of Z can be engineered by selecting resistor and capacitorvalues to determine a value of Z relative to R_(s).

FIG. 5 is a circuit diagram of an interface circuit 500. In FIG. 5,terminals 502 and 504 define an input voltage U_(i). An impedancecontrol circuit 506 is connected in series with a power supply circuit508.

In the impedance control circuit 506, a resistance R_(i) 510 isconnected in series with a voltage control device such as a zener diode514, both of which are connected in parallel with an inductance 512. Thepower supply circuit 508 is shown modeled as a second voltage regulationdevice such as a zener diode 516, which defines an output voltage U_(o),connected in series with a sense resistor R_(s) 518.

FIG. 6 is an impedance versus frequency graph for the circuits of FIGS.5 and 7. FIG. 6, shows that an impedance seen by a DC or low frequencysignal is the relatively low sense resistance of resistor R_(s), up tosome predetermined edge frequency f1. At frequency f1, the impedancebegins to increase until it flattens at a value equal to a resistance ofresistor R_(i) 510 in series with (i.e., added to) sense resistor R_(s)(shown in FIG. 6 as R_(s)+R_(i)). This frequency characteristic can beunderstood from examining circuit 500 of FIG. 5. Specifically,inductance 512 presents a short circuit to low frequency signals, whichallows the low frequency signals to bypass resistor R_(i) 510 andvoltage control device 514. At high frequencies, inductance 512 presentsan open circuit, thereby forcing high frequency components to traverseresistors R_(i) 510 and R_(s) 518.

FIG. 7 is a circuit diagram of an implementation 700 of the interfacecircuit of FIG. 5. In FIG. 7, a power supply circuit 702 is connected inparallel with a DC input voltage controller circuit 704. The DC powersupply circuit 702 includes a DC/DC converter 706, as well as inputresistance R_(i) 510.

The DC input voltage controller 704 includes a current sink 708, as wellas a resistor 710, a resistor 712, a capacitor 714, an operationalamplifier 716, and a resistor 718. Additionally, a DC output voltagecontrol circuit 720 may include a voltage regulation device such as azener diode 722, which serves to protect against excessive voltage atthe output U_(o).

In considering the circuit 700 of FIG. 7, it should be understood fromthe discussion above with respect to FIG. 5 that the parallelcombination of the DC input voltage controller 704 with the power supplycircuit 702 allows for a bypassing of an input current from an input ofthe power supply circuit 702 to an output of the circuit 702 forlow-frequency signals, while high frequency signals see only the passiveresistance of input resistor Ri 510.

FIGS. 8A and 8B are impedance versus frequency graphs for the circuit ofFIG. 7. More specifically, FIG. 8A is an impedance versus frequencygraph for the power supply circuit 702, and FIG. 8B is an impedanceversus frequency graph for the DC input voltage controller circuit 704.In FIG. 8A, the impedance characteristic of the power supply circuit 702is simply equivalent to a value of the resistor R_(i) 510 added to thesense resistance R_(s). In the implementation of FIG. 7, R_(i) is apassive element having a constant value. In contrast, in FIG. 8B, inputimpedance is stable at R_(s) below a cutoff frequency f1, and growssteadily higher after the cutoff frequency f1. Thus, it should beunderstood that combining the impedance versus frequency characteristicsshown in FIGS. 8A and 8B result in the combined impedance versusfrequency characteristic already discussed above with respect to FIG. 6.

The impedance versus frequency characteristics shown in FIGS. 6, 8A and8B are characteristics which provide low impedance to the 4–20 mA DCcurrent signal, while providing a relatively high and flat impedance toall frequencies above the cutoff frequency f1. Moreover, this impedanceversus frequency characteristic can be obtained reliably andinexpensively, since a minimum number of circuit components areutilized, and the communications impedance is provided by the passiveresistive element resistor R_(i) 510.

The presence of the DC input voltage controller 704 allows for themaintenance of a stable DC input voltage. This effect can be betterunderstood by considering an operation of the circuit 700 in the absenceof the DC input voltage controller 704. In this case, in considering avalue of the resistor R_(i) 510 to be, for example, 300 Ohms, then aninput voltage Ui would be increased by the voltage drop across theresistor R_(i) 510; i.e., a current magnitude of the current multipliedby, in this case, 300 Ohms. Thus, at 4 mA, there would be an additional1.2 volts added at the input voltage (i.e., 0.004 A×300 Ohms=1.2V). Inthe case of a 20 mA input current, however, the increase added by thevoltage drop across resistor R_(i) 510 would grow to be 6 volts (i.e.,0.002 A×300 Ohms=6V). With the presence of the DC input voltagecontroller 704, however, excess current above 4 mA, not needed by theload device such as actuator 112, is drawn from the input of the DC/DCconverter, so that only 1.2 volts may be added to the loop DC inputvoltage. In this way, the input voltage is stably maintained at, forexample, 10.2V (i.e., V_(in)+V_(Rj)=9V+1.2V=10.2V).

FIG. 9 is a circuit diagram of an interface circuit 900. FIG. 9 is verysimilar to FIG. 5, and includes input terminals 902 and 904 defining aninput voltage U_(i), as well as a impedance control and bypass circuit906 connected in series with a power supply circuit 908. The impedancecontrol and bypass circuit 906 includes a resistor R_(i) 910, aninductance 912, and a voltage control device 914, much like thecorresponding elements in FIG. 5. Additionally, however, the impedancecontrol and bypass circuit 906 also includes a negative impedance −R_(x)916. Power supply circuit 908, identically to the power supply circuit508 of FIG. 5, includes a voltage control device 918, and a senseresistor R_(s) 920.

FIG. 10 is an impedance versus frequency graph for the circuits of FIGS.9 and 12. In FIG. 10, it can be seen that the impedance of circuit 900of FIG. 9, much like the input impedance of the circuit 500 of FIG. 5,begins to grow rapidly above sense resistance R_(s) at a predeterminedcutoff frequency f1, and flattens at a value equal to a resistance ofR_(i) 910 for frequencies in a digital communication range. Unlikecircuit 500 of FIG. 5, however, as shown in FIG. 10, impedance 916actually imposes a negative impedance on very low frequency signalsreceived at the circuit 900.

Such a negative impedance characteristic provided by impedance 916 maybe used to compensate for undesirable voltage drops (and correspondingimpedances) which occur, for example, along a length of the two-wireinterface 108, or along a security barrier, or other element in serieswith the circuit 900 and having an impedance. More specifically, as aresult of such added, unwanted voltage drops seen by the current source(i.e., current source 104 in FIG. 1), an ac voltage on the currentsource output may be restricted from sufficiently increasing in a mannerconsistent with a signal being communicated from the current source 104.In such cases, communication signals on the loop wires may be corrupted.Decreasing the input voltage Ui with increasing current (i.e., negativeimpedance) essentially compensates this restriction. Moreover, since alow current signal on the two-wire interface 108 creates low voltagedrops, while a high current signal creates high voltage drops on anypositive loads on the wires, the device input may decrease the inputvoltage U_(i) with higher input current, even while sufficient operatingpower on the device input is stably maintained, as discussed in moredetail below.

One way to achieve negative impedance 916 is to create an inverserelationship between the DC input voltage U_(i) and the input currentitself. In other words, as the DC input voltage increases, the inputcurrent decreases, which is equivalent to a negative impedance.

FIG. 11 is a voltage versus current graph for the circuits of FIGS. 9and 12. In FIG. 11, as just described, increasing current I_(i) resultsin decreasing voltage U_(i), down to a low limit level equivalent toUo-Limit, i.e., the output voltage minus some predetermined limit leveldesigned to protect against overheating. Thus, in contrast to thecircuits of FIGS. 5 and 7, the DC input voltage of FIGS. 9 and 12 is notstable, and, as shown, in fact decreases with increasing current.

FIG. 12 is a circuit diagram of an implementation 1200 of the interfacecircuit of FIG. 9. In FIG. 12, circuit 1200 includes an impedancecontrol and power supply circuit 1202, the DC input voltage controller1204, and a frequency compensation circuit 1206. The impedance controland power supply circuit 1202 includes a DC/DC converter 1208, as wellas the input resistor R_(i) 910. As explained above with respect toFIGS. 5 and 7, the resistance R_(i) 910 is presented to all AC currentsignals in the digital communication spectrum above the cutoff frequencyfl.

The DC input voltage controller 1204 includes a current bypass 1210, aresistor 1212, a resistor 1214, a capacitor 1216, a resistor 1218, andan operational amplifier 1220. As with the DC input voltage controllerdiscussed above with respect to FIG. 7, DC input voltage controller 1204serves to draw current that exceeds the 4 mA minimum value away from theDC/DC converter 1208.

The frequency compensation circuit 1206 includes a resistor 1222, acapacitor 1224, a capacitance 1226, a resistor 1228, and a resistor1230. Frequency compensation circuit 1206 is needed due to the fact thatresistor 1230 (as opposed to resistor 718, see FIG. 7) measures avoltage difference between a positive terminal input to opamp 1220 andthe negative rail 904 (as opposed a difference between the positiveterminal input and ground); As a result, and since the opamps 436, 716,and 1220 all attempt to obtain a zero voltage differential at theirinput terminals, opamp 1220 must respond to an increased negative valueat rail 904 (due to, for example, increased current) by increasing avoltage value at the rail 902. In this way, a fixed relation can beobtained between an input current (i.e., voltage at negative rail 904)and voltage at rail 902. However, because the input current/voltage atrail 904 is related to an AC value of the input current, the opamp 1220might transfer this AC value to the rail 902, as well. The frequencycompensation circuit 1206, by selecting appropriate values for resistor1222 and capacitor 1224 relative to resistor 1230 and resistor 1228,filters these AC components from the rail 902. Thus, the frequencycompensation circuit 1206 allows an increase in impedance of DC inputvoltage controller 1204 at higher frequencies, which is the desiredbehavior for circuit 1200, as explained above.

As shown in FIG. 12, the reference voltage for the operational amplifier1220 has a dependence on the sense resistor 920, such that the referencevoltage changes with the input current. Moreover, the input of theoperational amplifier 1220 compared against the reference voltage isalso dependent on the input current, as shown by the connection ofresistor 1230 to terminal 904 (as opposed to a connection of resistor718 to ground in FIG. 7). The extent to which the reference voltagechanges with the input current depends upon the resistors 1212, 1214,1218, 1228, and 1224.

More specifically, the input voltage can be defined by the equation (1):

$\begin{matrix}{U_{i} = {{U_{r}\left\{ \frac{\left\lbrack {{\left( {R_{1} + R_{2} + R_{3}} \right)\left( {R_{4} + R_{5} + R_{S}} \right)R_{5}} + {R_{3}R_{5}R_{S}} - {\left( {R_{1} + R_{2}} \right)R_{4}R_{S}}} \right\rbrack}{\left\lbrack {{R_{3}\left( {R_{4} + R_{5} + R_{S}} \right)}\left( {R_{4} + R_{5}} \right)} \right\rbrack} \right\}} - {I_{i}R_{S}\left\{ \frac{\left\lbrack {{R_{4}\left( {R_{1} + R_{2} + R_{3}} \right)} - {R_{3}\left( {R_{4} + R_{5}} \right)}} \right\rbrack}{\left\lbrack {R_{3}\left( {R_{4} + R_{5} + R_{S}} \right)} \right\rbrack} \right\}}}} & (1)\end{matrix}$In equation (1), it can be seen that an increase of current I_(i) willresult in a decrease in U_(i) when the term R4*(R1+R2+R3) is higher thanthe term R3*(R4+R5), in the numerator of the second term in thedifference. This relationship can also be expressed as R4*(R1+R2)>R3*R5,due to the presence of the term R3*R4 in both terms.

Thus, in equation (1) and referring back to FIG. 11, U_(i) will betheoretically maximized when I_(i) is zero; however, in this case powerto a load device will also be zero (since Power=I_(i)*U_(i)=0). When thecurrent I_(i) reaches a point where a necessary level of power isreached (typically, a point slightly below 4 mA), then equation (1)governs and the relationship between U_(i) and I_(i) in FIG. 11 isdemonstrated. When the current I_(i) exceeds the limit of 20 mA, anyexcess current causes U_(i), theoretically, to reduce to zero andthereby protect the circuit 1200 and associated wiring from overheating.While theoretically the input voltage goes to zero as just described,this behavior may not actually exist. For example, a technique fordecreasing the input voltage U_(i) such as sinking the current from theinput to the output (e.g. with a transistor) will only work until alevel of the output voltage is reached, whereupon a further increase ofinput current will increase the power to the circuit 1200.

In such a case, it may occur that U_(i) will increase with currentbeyond 20 mA, thereby presenting the possibility of overheating. Toavoid this circumstance, an impedance circuit may be added at theconnection defined by terminals 902 and 904 that effectively shuts offthe input current I_(i) at some value above 20 mA, such as, for example,23 mA. Such a circuit may be designed to present little or no impedancebeneath the cut-off value of, for example, 23 mA, but to presentextremely high impedance above this cut-off value. In this case, powerto the field device 110 and related circuitry is effectively and safelylimited.

Thus, in contrast to the circuits 400 and 700, circuit 1200 does notrely on the device load to determine a magnitude of the current to bebypassed; rather, an amount of output current to be bypassed ispredetermined with respect to a particular input current. As long as theoutput current for all input currents is sufficient to drive the loaddevice(s), the circuit 1200 will be operational. In cases where theoutput current exceeds the level necessary to drive the load device(s),a DC output voltage control circuit 1232 having a voltage regulationdevice such as a zener diode 1234 may be used to sink the excesscurrent.

Moreover, in contrast to the circuit 700, the DC input voltage is notheld stable at a predetermined value for various input currents. Rather,the DC input voltage decreases with an increasing input current, therebyproviding the negative impedance characteristic discussed above.

In FIGS. 4, 7, and 12, it is assumed that the various DC/DC convertersare of the type which are capable of driving current forward andbackward through the converter, which are discussed above with respectto U.S. Pat. No. 6,064,583. Accordingly, the DC input voltage controllercircuit 1204 can not only bypass excess current from an input of theDC/DC converter 1208, it also may redirect current back through theDC/DC converter 1208 and over the resistor R_(i) 910 and the two-wireinterface 108 (defined in FIG. 12 by terminals 902 and 904). Thiscurrent, opposing the flow of current of the 4–20 mA signal as describedabove, has the affect of providing the negative impedance to theincoming current signal, thereby compensating for any undesired voltagedrops which occur at any impedances which may be in series with theinterface circuit 1200.

FIGS. 13A and 13B are impedance versus frequency graphs for the circuitof FIG. 12. FIG. 13A shows that, for all frequencies, an impedance thatexceeds the impedance controller and power supply circuit 1202 isequivalent to the value of the resistance R_(i) 910 added to theresistance of the sense resistor 920 R_(s) 920. In FIG. 13B, thenegative impedance 916 −R_(x) is in existance at very low frequencyranges, and grows to R_(s). At the cutoff frequency f1, the impedancegrows indefinitely for the DC input voltage controller circuit 1204.Thus, a combination of the graphs of FIGS. 13A and 13B yields theimpedance versus frequency graph shown in FIG. 10.

As an additional advantage, the reverse current that is present in theoperation of circuit 1200 can be additionally used to provide digitalcommunication and redirection of communicator 130 (FIG. 1). In general,transmissions from a circuit such as circuit 400, 700, or 1200 may beperformed by voltage modulation. However, in circuit 1200, the reversecurrent may be modulated as it is output from the DC/DC converter 1208and routed through resistance R_(i) 910, thereby allowing digitalcommunications via this modulated current signal. Of course, thistechnique for digital communications is only available in situationswhere the input current exceeds 4 mA and the excess is not needed in itsentirety to drive the load device (i.e., when the input voltagecontroller circuit 1204 is bypassing current).

In conclusion, implementations have been disclosed which inexpensivelyand reliably provide a 4–20 mA interface circuit having a dual impedancecharacteristic such that a first impedance is presented to a firstcurrent signal, and a second impedance is presented to a second currentsignal. For example, the first impedance may be a low passiveresistance, and the first current signal may be a DC 4–20 mA currentsignal. The second impedance may be a higher passive resistance, and thesecond current signal may be an approximately 1 mA peak-to-peak ACsignal imposed on the 4–20 mA current signal for carrying digitalcommunications. As described, the first impedance may be a senseresistor, and a voltage across the sense resistor serves to measure acurrent magnitude of the 4–20 mA signal. The second impedance may be oneor more resistors in series with a power supply circuit such as a DC/DCconverter, where a resistance of these resistors is added to aresistance of the sense resistor.

In order to present the dual impedances to the two current signals asjust described, the second impedance may be placed in series with thepower supply circuit, and this series combination may be placed inparallel to a current bypass circuit having an inductive electricalcharacteristic. This combination of the second impedance, power supplycircuit, and current bypass circuit may then be placed in series withthe first impedance. In this implementation, low-frequency signals suchas the 4–20 mA current signal are short-circuited around the secondimpedance and power supply circuit, seeing only the first impedance(e.g., sense resister). In contrast, high-frequency signals see theeffectively open-circuit inductive current bypass circuit, and see thefirst and second impedances in series with one another.

When the 4–20 mA signal exceeds a pre-determined current value minimumof, for example, 4 mA, and the excess is not required by a load deviceassociated with the interface circuit, the current bypass circuit maysink the excess current to ground. Alternatively, routing of such excesscurrent may be made dependent upon the voltage across the firstimpedance (e.g., the sense resistor), so that an output current is fixedto a pre-determined amount corresponding to the value of the inputcurrent. In this case, the excess current may be driven through thepower supply circuit and back onto a two-wire interface associated withthe interface circuit, to provide the interface circuit with a negativeimpedance characteristic. This negative impedance characteristic may beused to compensate for unwanted voltage drops associated with thetwo-wire interface. Additionally, the current driven back through thepower supply circuit may be used to transmit digital communications fromthe interface circuit over the two-wire interface.

A number of implementations have been described. Nevertheless, it willbe understood that various modifications may be made. Accordingly, otherimplementations are within the scope of the following claims.

1. A circuit comprising: a two-wire interface operable to input alow-frequency, first current and a high-frequency, second current; afirst impedance presented to the first current; a second impedancepresented to the second current; a DC supply circuit in series with thesecond impedance to thereby form a series combination; and a currentbypass circuit in parallel with the series combination and operable tobypass a portion of the first current around the series combination. 2.The circuit of claim 1 wherein the first impedance is a sense resistanceoperable to transmit the first current, such that a device variable of adevice external to the circuit is set according to a sense voltageacross the sense resistance and proportional to the first current. 3.The circuit of claim 1 wherein the first impedance is in series with theparallel combination of the current bypass circuit and the seriescombination.
 4. The circuit of claim 1 wherein the first impedance isadditionally presented to the second current.
 5. The circuit of claim 1wherein the second impedance comprises a passive resistive element. 6.The circuit of claim 1 wherein the DC supply circuit comprises a DC/DCconverter operable to drive current forwards and backwards therethrough.7. The circuit of claim 1 wherein the portion of the first current isdetermined based on a difference between a magnitude of the firstcurrent and an amount of drive current required to drive a load device.8. The circuit of claim 1 wherein the current bypass circuit is operableto maintain a stable DC voltage at the two-wire interface.
 9. Thecircuit of claim 1 wherein the portion of the first current isdetermined based on a magnitude of the first current, thereby forming apre-determined relationship between an output current of the circuit andthe first current.
 10. The circuit of claim 9 wherein the magnitude ofthe first current is measured at the first impedance.
 11. The circuit ofclaim 9 wherein an input voltage measured at the two-wire interfaceincreases with a decrease in the first current.
 12. The circuit of claim9 wherein the circuit presents a negative impedance at the two wireinterface.
 13. The circuit of claim 9 wherein the portion of the currentis driven through the DC supply circuit and output through the two-wireinterface.
 14. The circuit of claim 1 wherein the first current has afrequency below approximately 500 Hz.
 15. The circuit of claim 1 whereinthe second current is super-imposed over the first current and carries adigital communications signal.
 16. A circuit comprising: a firstimpedance; a second impedance; a DC/DC converter in series with thesecond impedance and forming a series combination; and a current bypasscircuit in parallel to the series combination and operable to presentthe first impedance to a low-frequency, 4–20 mA first current, andfurther operable to present the second impedance to a high frequencysecond current, the second current carrying a digital communicationssignal and superimposed on the first current.
 17. The circuit of claim16 wherein the first impedance includes a sense resistor.
 18. Thecircuit of claim 16 wherein the current bypass circuit presents both thefirst impedance and the second impedance to the second current.
 19. Thecircuit of claim 16 wherein the first impedance comprises a negativeimpedance resulting from a reverse current driven from the currentbypass circuit through the DC/DC converter and the second impedance. 20.The circuit of claim 19 wherein a magnitude of the reverse current isbased on a voltage across a sense resistor, the voltage beingproportional to the first current.
 21. The circuit of claim 16 wherein aportion of the first current is used to power a device external to thecircuit.
 22. The circuit of claim 21 wherein a portion of the firstcurrent not required to power the device is shunted to ground by thecurrent bypass circuit, thereby maintaining a circuit input voltage at astable value.